Resistive random access memory (ReRAMs) are known as one of nonvolatile semiconductor storage devices. In ReRAMs, a memory cell includes a variable-resistance layer and a diode which are connected in series, and electrodes holding them therebetween. Each memory cell is connected at one end to a word line, and connected at the other end to a bit line. The internal physical structure of the variable-resistance layer is changed by voltage or current applied thereto, and the resistance thereof is also changed according to the physical structure. One of the two states where the variable-resistance layer has two different resistances is used as the state in which “0” data or “1” data is held, which enables storage of data. Since the state of resistance is maintained even after power supply to the variable-resistance layer is stopped, ReRAMs are nonvolatile memories.
A memory cell array of ReRAMs may include an operation cell area and a dummy cell area. The dummy cell area is an area which runs along edges of the memory cell array, encloses the normal cell area, and serves as a cushion on the boundary between the memory cell array and the outside thereof. Cells located in the dummy cell area are not used as memory. Peripheral circuits and the memory cell array are processed by different processes, and the memory cell array has a structure finer than that of the peripheral circuits and thus is different to be processed. Therefore, memory cells located along edges of the memory cell array are apt to be inferior. These parts which are apt to be inferior are used as dummy area, which enables maintaining a high yield in the operation cell area. The dummy cell area is provided with dummy cells, dummy bit lines, dummy word lines, bit lines, and word lines. The dummy cell area and the normal cell area share the bit lines and the word lines, while the dummy bit lines and the dummy word lines only exist in the dummy cell area.
As described above, both ends of each memory cell are connected to the bit line and the word line, respectively. In addition, to achieve high integration, a structure may be used where memory cells are vertically stacked up with word lines or bit lines interposed two stacked memory cells. In such a structure, memory cells are mutually connected through bit lines, word lines, dummy bit lines, or dummy word lines. When cells made defective by any causes function as simple conductors, a leakage current may be undesirably transmitted to a wide range according to the positions of the defective cells. This impedes application of a desired voltage to a target memory cell, and deteriorates the operation margin of the ReRAM.